1. Field of the Invention
This invention relates to automated semiconductor test equipment and, more particularly, to debug facilities for use with automated semiconductor test equipment.
2. Description of the Relevant Art
Integrated circuits are widely used in a variety of products, from computer systems to automobiles. Integrated circuits embody a variety of electrical components (such as transistors, capacitors, and resistors) on a single monolithic semiconductor substrate. By combining these individual electrical components into a single device, manufacturing costs for the product and the size of the product are decreased. Manufacturing costs are decreased because the product contains fewer discrete components (to purchase and to assemble). Size is decreased because electrical components fabricated within an integrated circuit may be placed closer together than a similar set of discrete electrical components.
Integrated circuits are fabricated through a multi-step process. Impurities are selectively implanted into areas of a highly purified semiconductor substrate. Thereafter metal conductors are patterned across the surface of the semiconductor substrate. Metal conductors extend between implant regions to form the monolithic electrical circuit. Typically, multiple copies of the integrated circuit are fabricated simultaneously on a single semiconductor substrate, referred to as a wafer. After fabrication, the individual integrated circuits are "diced". Dicing is the process of separating the integrated circuits from each other and the remaining portions of the wafer. Individual integrated circuits are packaged in one of many types of integrated circuit packages. The packages protect the integrated circuit from automated assembly machines that are typically used to place the integrated circuit into a product. Packages also provide an electrical connection in the form of pins which extend from the package. The pins are often subjected to more stressful conditions than the packaged integrated circuit. For example, pins are designed to withstand high insertion forces and high solder temperatures, while a semiconductor substrate is generally protected within the package from such conditions.
The pins of an integrated circuit package are connected to input/output bonding pads on the integrated circuit substrate. Input/output bonding pads are relatively large areas of conductive material formed onto the integrated circuit during metallization. The input/output bonding pads are electrically connected to circuits on the integrated circuit substrate via metal conductors. These circuits provide communicative signals to devices that may be connected to the integrated circuit when it is used in a product.
As with many manufactured devices, some integrated circuits will not function properly when manufactured. Defects may be introduced during any of the fabrication steps such as implantation, metallization, dicing, etc. Defects may also occur during packaging. Therefore, integrated circuits are tested before they are used in products. Furthermore, integrated circuits are tested after fabrication but prior to being packaged (i.e. while the integrated circuits are still a part of the wafer). In the latter instance, packaging costs are saved if defective integrated circuits are discovered and not packaged. It is noted that once an integrated circuit is packaged, it typically cannot be removed from the package without destroying the package. Post-packaging testing is still employed even after individual die are tested as part of a wafer. Post-packaging tests are desirable to more fully determine circuit operability, but also detect damage possibly resulting from packaging.
Automated semiconductor test equipment is employed to test integrated circuit die while still a part of the wafer and after being packaged. Testing performed upon integrated circuits which are still a part of a wafer is referred to as wafer test, and post-packaging testing is referred to as chip test. Several tests are performed by the automated semiconductor testing equipment, including: power pin short tests, pin short tests, pin open tests, functional Vcc min/max tests, leakage current tests, Vol/Voh tests, static Icc tests, and dynamic Icc tests.
Power pin short tests check for electrical shorts from power supply pins (or power supply input/output pads in wafer test) to other pins or to ground. If a power supply pin is shorted, the circuits connected to that power supply pin will not function. Therefore, the integrated circuit is defective.
Pin short tests (or pad short tests in wafer test) check for signal pins that are shorted to other pins or to ground or power supply pins. A signal pin (or pad) is a pin (or pad) which conveys an electrical signal during use. Signal pins that are shorted will not convey the correct signal from the integrated circuit, and so the integrated circuit is defective.
Pin open tests (pad open tests in wafer test) check for pins that are not connected correctly such that no electrical current may flow from the pin to the pad or from the pad to the circuits embodied within the integrated circuit. If a pin is open, then it will not convey the correct signal from the integrated circuit, and so the integrated circuit is defective.
Functional Vcc min/max tests first power the integrated circuit with a power supply voltage at the minimum and maximum value specified for the integrated circuit. The integrated circuit is expected to operate properly within a power supply voltage range bound by the specified minimum and maximum values. Functional patterns of signals are applied to the input/output pins (pads) of the integrated circuit and expected results on other pins (pads) are checked. Functional patterns are sequential patterns of input signals which represent a sequence of input signals that might be applied to the integrated circuit when in use within a product, along with the expected sequence of output signals that the integrated circuit should produce if operating properly. If a result does not match the expected value, then the integrated circuit does not function properly within its specified power supply range. Therefore, the integrated circuit is defective.
Leakage current tests are typically applied to an integrated circuit which is powered and held in reset state. None of the internal circuits of the integrated circuit are switching in this configuration, so the electrical current that may be drawn by the integrated circuit is leakage current associated with transistors embodied upon the integrated circuit. If the measured leakage current is larger than a specified amount (typically a few microamperes), then the integrated circuit is defective.
Vol/Voh tests check the voltages that are produced on each output pin (or pad in wafer test). Vol/Voh tests ensure that the voltage level conveyed on a particular output pin is below a Vol level specified for the integrated circuit when the pin is conveying a logical zero value. Additionally, Vol/Voh tests ensure that the voltage level conveyed on a particular output pin is above a Voh level specified for the integrated circuit when the pin is conveying a logical one value.
Static and dynamic Icc tests check the current drawn from the power supply pins by an integrated circuit. If the current drawn is above a level specified for the integrated circuit, then the integrated circuit is deemed defective. A static Icc test is performed upon an integrated circuit after appropriate voltages have been applied to its power and ground pins and the integrated circuit has been reset to an idle state. The inputs to the integrated circuit are held constant (including the clocking input) and the current is measured. Conversely, a dynamic Icc test is performed upon an integrated circuit while the test equipment repeatedly performs a test designed to cause as many transistors as possible to switch within the integrated circuit. The dynamic current is measured several times and averaged.
The above tests are but a few of the many possible tests useable upon a wafer or chip. Tests are chosen depending upon the applicability of the product within which the integrated circuit is placed. Additional tests will not be discussed for sake of brevity, however, it is understood that any test procedure initiated by any type of test equipment falls within the spirit and scope of the present discussion.
When a relatively large number of integrated circuits are being found defective at wafer test or at chip test, then debugging needs to be performed to determine the cause of these defects. Also, when a newly designed integrated circuit is being fabricated for the first time, a large number of defects may indicate a significant problem with the new design or a problem with interfacing to the automated semiconductor test equipment. Sometimes, the test equipment is not aligned to the integrated circuit correctly. If a proper electrical connection is not made between the test equipment and the integrated circuit, then tests will indicate defects even though the integrated circuit is not defective.
Unfortunately, typical automated semiconductor test equipment provides only a limited debug capability. For example, automated test equipment often provides an oscilloscope to observe voltage and current levels on various pins (or pads). However, the oscilloscope is typically located a large distance from the integrated circuit being tested (referred to as the device under test, or "DUT"). The long electrical leads connecting the oscilloscope to the DUT have an associated large inductive impedance which limits the frequency at which values may be sensed. The frequency limits might be quite severe depending upon the length of the electrical leads. It is not uncommon to encounter a 25 MHz upper frequency limit for testers having the oscilloscope displaced from the DUT by several feet. Modern integrated circuits, however, are being designed with an emphasis on speed. Clock frequencies of the core devices routinely operate at speeds exceeding, for example, 25 MHz. Accordingly, conventional debugging capabilities are insufficient for high speed devices. Additionally, debug devices such as oscilloscopes and logic analyzers cannot be connected to the DUT directly due to the configuration of the tester interface apparatus, as will be described below. It is desirable that the test equipment be enhanced to allow a more advanced level of debugging.